The on-going demand for high performance portable electronic systems having long battery lifetimes has driven the need for ever higher performance at ever lower operating power. Those demands often conflict: higher performance tends to require higher power while long battery lifetimes tend to be associated with lower performance.
A direct approach to achieving higher performance and longer battery lifetimes is simply to use longer life batteries. This creates the problem that for a given battery chemistry greater battery energy storage requires larger and heavier batteries. Eventually both battery size and weight increase to the point that they become unacceptable in a given system.
Another approach to achieving higher performance and longer battery lifetimes is to incorporate effective designs. In fact effective designs are critical in many synchronous Application Specific Integrated Circuits (ASICs) and System-on-Chips (SOCs) devices.
Since almost all modern electronic system designs are clocked one area that is well suited for effective designs are clock distribution networks. In a clocked system gate operations are synchronized by clock signals. So long as the gates can keep up with the clock the higher the clock rate the faster the performance. Unfortunately high speed clocking consumes a great deal of power. In fact, the on-chip clock distribution network (hereinafter “CDN” for convenience) of modern very large scale integrated circuit (hereinafter “VLSI circuits” for convenience) often consumes more than 35% of the total chip power and can occasionally require as much as 70%.
Prior art VLSI circuit designs tended to focus on reducing the lengths of interconnects such as global buses and CDNs by increasing device density. This reduced path lengths, which reduced resistances which reduced power consumption. But since higher densities enabled increased clock speeds power consumption also increased.
In prior art VLSI circuit CDNs are almost always voltage-mode operated. That is, a clock drove clocked devices using voltage levels. In CMOS technology the applied logic levels are ideally zero and Vdd (usually the applied power supply voltage) but in practice slightly different logic levels induce switching. This “voltage mode” switching is currently and for decades has been the de facto standard in logic families.
While voltage mode switching has been an enabling technology in modern electronics its limitations are becoming apparent. Switching logic level inputs invariably requires driving a capacitance to either charge or discharge. To avoid noise problems and to maintain reliable device switching the voltage difference between a HIGH logic level (ideally Vdd) and a LOW logic level (ideally zero) can only be minimized so much. Thus a driven capacitance must be charged or discharged over a rather large voltage step. The result is that both the achievable performance and power reduction in voltage mode clocked device designs are limited.
However, prior to and in early CMOS technologies current-mode (hereinafter “CM”) logic was a viable alternative approach used for high-speed signaling. Reference, for example, M, Yamashina and H, Yamada, “An MOS current mode logic (MCML) circuit for low-power sub-GHz processors.” IEICE Transactions On Electronics, E75-C(10): 1181-1187. 1992. That publication is hereby incorporated by reference for all purposes to the full extent allowable by law.
CM logic, sometimes referred to as source-coupled logic has been successfully used for interfacing with fiber optical systems and other high-speed data devices. CM logic circuits can be made very fast because they operate using a lower voltage swing than comparable voltage mode logic circuits. This makes CM logic switching interesting when confronted with the power and variability problems of voltage mode switching.
FIG. 1 illustrates a prior art CM logic circuit 100. That CM logic circuit 100 incorporates a voltage mode input transmitter (Tx) 102 that transmits a current having a minimal voltage swing onto an interconnect 104 such as a transmission line. A transimpedance amp receiver (Rx) 106 converts the received current into a full-swing output voltage using a current-to-voltage converter. The CM logic circuit 100 reduces delays over voltage mode schemes at the cost of larger signal skews that result from small shifts in the receiver (Rx) 106 voltage swings relative to a common-mode reference voltage. Other researchers have implemented somewhat different CM logic schemes. However, all such schemes have problems such as rise and fall-time mismatches and large static and dynamic power consumptions.
However, in CM logic switching the required static power is often significantly less than the dynamic power required in voltage mode logic switching. In addition, device latency can be significantly improved using CM logic switching. CM logic switching may also improve reliability since they are less susceptible to single-event transient spikes and have reduced heat generation.
Therefore, CM logic switching in clock distribution networks would be beneficial. Preferably, such a CM logic clock distribution network would implement current mode clocking devices. CM operated flip-flops that are suitable for incorporation at the chip level for clock distribution would be highly advantageous. VLSI devices that use CM flip-flop clocking devices in CDNs would be particularly valuable. High fan out symmetric CM distribution trees having multiple CM flip-flips would be particularly useful.